Integrated circuits are often formed in arrays wherein the same Metal-Oxide Semiconductor (MOS) device geometry is repeated multiple times across a reticle field. The performance of the integrated circuit is dependent upon pattern uniformity between the shapes that comprise functional components within the MOS devices within the array in order to ensure matching of their electrical characteristics. Pattern uniformity of the shapes at the edge of the array is sensitive to density of the background circuitry, because there is a density gradient between the edge of the array and the background circuitry. The existing solution is to add a buffer zone of dummy devices which are identical to the MOS device, but not electrically active. The buffer zone results in better pattern uniformity of the active MOS devices within the array, but can add significant area overhead to a chip.